Job Overview: We are looking for skilled PCIe Verification Engineers and Leads to join our team. Candidates should have expertise in System Verilog, UVM, and coverage-driven verification processes. Engineers will contribute to test development and debugging, while Leads will drive the verification process, manage teams, and ensure the successful sign-off of PCIe projects. Both roles will involve working on cutting-edge PCIe and AXI technologies.
Key Responsibilities
1. Engineer:
1. Develop test benches and detailed test plans for PCIe verification.
2. Use System Verilog and UVM to write, simulate, and debug test cases.
3. Perform coverage analysis to ensure thorough verification.
4. Work collaboratively with design and cross-functional teams to resolve issues.
2. Lead:
1. Lead the entire verification process for PCIe projects.
2. Mentor and guide a team of verification engineers, ensuring timely and high-quality outputs.
3. Define and manage test strategies, simulation plans, and coverage analysis.
4. Act as the key decision-maker for verification sign-off, working closely with management and design teams.
Key Skills
Expertise in System Verilog, UVM, and coverage-driven verification methodologies.
Strong experience in test planning, test bench development, simulation, and debugging.
For Lead: Proven leadership, team management, and decision-making capabilities.
Domain Knowledge
Deep understanding of PCIe protocols.
Experience with AXI (Advanced eXtensible Interface).
Qualifications
1. For Engineer: 5+ years of experience in PCIe verification and hardware validation.
2. For Lead: 10+ years of experience in PCIe verification, with a demonstrated ability to lead teams and projects.
3. Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
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