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Client:
Riverlane
Location:
Cambridgeshire, United Kingdom
Job Category:
-
EU work permit required:
Yes
Job Reference:
dbdeef9c6976
Job Views:
9
Posted:
03.03.2025
Expiry Date:
17.04.2025
Job Description:
Cambridge, UK | Full-time or Part-time | Permanent | Salary: £75,000 to £100,000 DOE
We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
About us
Riverlane’s mission is to make quantum computing useful, sooner. From climate change to healthcare, large and reliable quantum computers will help solve some of the world’s important challenges. Riverlane is building the quantum error correction stack to make this happen. It’s a complex problem that requires a range of skills, talent and passion. We’re making remarkable progress and growing fast.
About the role
We have a fantastic opportunity for an experienced Digital Design Engineer to join us as we build the world’s first quantum error correction (QEC) stack. Don’t have a background in quantum computing? Not a problem! This cutting-edge technology requires a wide range of skills and disciplines, including classical computing skills. You will learn quantum computing along the way.
As Senior Digital Design Engineer at Riverlane, you will help develop a multi-FPGA, low-latency, high throughput system that needs to perform complex operations in a predictable and guaranteed way. You will use your knowledge and expertise to support more junior engineers, interact with software and identify novel solutions to our challenging problems.
Our mission is exciting, but complex. It requires teams with a wide range of skills and perspectives, that communicate well and collaborate effectively to achieve truly innovative solutions.
You will thrive in an environment where knowledge sharing and continuous learning are the norm. We are moving fast in a brand new market, where requirements can change as the technology evolves, so the ability to adapt is important.
What you will do
As a Senior Digital Design Engineer at Riverlane, you will work on one of these key areas:
* Implementation of QEC decoders on hardware;
* Implementation of low-latency, high throughput data movement between cards and IPs; or
* Design of low-latency interfaces to bring data into the systems.
In all of the above, you will (often from scratch) design or integrate complex IPs and develop tests, collaborating closely with our Software, Verification and Testing experts to deliver an outstanding product.
Requirements
What we need
* Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)
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