We are seeking an experienced engineer to lead the verification of complex units within a project, overseeing all phases of the design and verification process.
Enhancing existing testbenches to improve performance, quality, and efficiency.
Testing and debugging Verilog RTL designs.
Planning and tracking verification tasks to meet project timelines and milestones.
Driving execution to ensure high-quality design outcomes and timely delivery.
Mentoring and coaching junior engineers.
Proficiency in hardware verification languages, ideally SystemVerilog/UVM.
Proficiency in scripting languages such as Python or Perl.
Strong software engineering background, including object-oriented programming, data structures, and algorithms.
Competency in C/C++ or Assembly programming, preferably for Arm architectures.
Proficiency in hardware design languages, such as Verilog.
Understanding of computer architecture fundamentals.
Familiarity with the entire design lifecycle, including concept, specification, implementation, testing, and documentation.
Previous experience in team leadership, including task planning and management.
This role offers a chance to work on cutting-edge projects and play a pivotal role in the design and verification of high-performance systems.
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