Job Title : Senior DFT Engineer Location : UK (Oxford or Bristol) Contract Type : Full-time, permanent position (Hybrid Working)
Salary: £75,000- £100,000 (Depending on experience)
Summary : My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/ SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/ SoC designs, including power management, memories, and Analog IP elements.
This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications.
Responsibilities :
1. Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs.
2. Offer consultancy on test-related issues to clients during pre-sales and implementation phases.
3. Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation.
4. Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process.
5. Ensure customer fault-coverage expectations and requirements are met.
6. Act as the primary contact between the company and any sub-contracted back-end service providers.
7. Create test specification documentation for sub-contractors providing test services.
8. Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services.
Key Skills / Experience :
Essential :
9. A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university.
10. 5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects.
11. Strong skills in DFT implementation, including:
12. Architectural specification
13. Tool-based and manual implementation
14. IP integration, including CPUs, Analog Macros, and IO PHYs
15. BIST and memory repair integration
16. Coverage analysis and improvement
17. ATPG, manual, and semi-automatic TPG, including simulation-based methods
18. At-speed test methodologies
19. DFT for power-managed designs
20. Generation of STA and scenario/ mode constraints
21. Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite).
22. Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus.
23. Experience with the complete SoC design flow and associated tools and methodologies.
24. Experience with RTL and gate-level simulations and related debugging for DFT verification.
25. VHDL/ Verilog coding skills.
26. Experience working with test service providers, including test hardware and program specification, bring-up, and debug.
Personality :
27. Excellent communication and interpersonal skills.
28. Strong presentation skills, capable of interacting with senior management.
29. Self-motivated with a strong customer service orientation and a 'can-do' attitude.
30. Creative problem-solving abilities.
31. Team player.
32. Ability to thrive in a dynamic environment.
What is on offer?
33. Starting salary of up to £100,000
34. Flexible hybrid working (Fully remote possibility)
35. Individual/ company performance Bonus scheme 15% of your basic
36. Company Share scheme
37. Matched pension contribution of 5%
And much more!
If this role is of interest, please apply with your most up to date CV.
To find out more about Computer Futures please visit www.computerfutures.com
Computer Futures, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 8 Bishopsgate, London, EC2N 4BQ, United Kingdom | Partnership Number | OC387148 England and Wales