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[CONTRACT] UVM Verification Engineer, Cambridge
Client:
microTECH Global Ltd
Location:
Cambridge, United Kingdom
EU work permit required:
Yes
Job Reference:
1bfb4ef19bb0
Job Views:
4
Posted:
18.04.2025
Expiry Date:
02.06.2025
Job Description:
Job Title: UVM Verification Engineer
Location: UK/Remote
Duration: 12 months' initial
Start Date: 1st July
A client based in the UK is looking for a UVM Verification Engineer for an initial 12 month contract with extensions. The role can be performed mainly remotely with up to 50% on-site ideally required.
The successful Verification Engineer will be joining a newly formed team within our client's offices and will help to expand on projects being worked on, both new and existing within other teams. You will be involved in new and existing ASIC projects.
Skills:
1. Strong background in ASIC Verification
2. System Verilog/UVM
3. SystemVerilog
4. Verification Planning
5. Experience with complex ASIC and/or large FPGA designs
Desirable Knowledge:
1. C/C++
2. Formal Verification
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