Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)
Responsibilities:
1. Develop micro architecture for the digital section of the ASIC.
2. Write RTL in Verilog for the blocks and simulate them.
3. Supervise the verification team and ensure they have sufficient coverage.
4. Develop SDC files for the backend.
5. Interact with the backend engineers to ensure the design meets all requirements such as STA, IR, etc.
Qualifications:
1. MS or PhD in Electrical Engineering.
2. 10 years of experience in digital design from specs to architecture, design, bench testing, and all the way to high volume production.
3. Deep understanding of RTL design for high speed datapath and signal processing, experience with different bus architectures, MCU integration.
4. Knowledge of the backend flow and ability to check STA reports and resolve any issues that require RTL change.
5. Ability to supervise the verification effort.
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