Job Title: DVEngineer [ASICSEngineering - Engineer]Remote6 month contract (High possibility of it getting extended)
Experience in UVM, Soc Methodology, Experience in developing test plans, test benches, AMBA Protocol, Debugging exp, exp with c model and language
Formal Verification - Nyc to have
Candidate requirements :
1. Experience in design and verification on SoCs and SoC Methodologies for verifying complex units on SoC using industry standard tools and technologies.
2. Proficient in developing unit and subsystem level test benches using SV/UVM methodology.
3. Constrained random and Metrics driven verification.
4. Experienced with C model integration and scorebording
5. FW code integration verification
6. Experience with AMBA protocols and BUS interconnect functional and formal verification along with coverage closure.
7. Experience with power aware verification and clock domain crossing verification.
8. Experience with debugging test failures
9. Strong knowledge of verification planning, coverage analysis, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
10. Experience with Verilog, C/C++, System C, TCL/Perl/shell-scripting
11. Strong analytical skills and ability to work in a dynamic and fast paced team environment.