This is an opportunity for an experienced Analog Layout Engineer to work for a well-established leader in energy-efficient chip-to-chip link solutions. For this position, you can be based in either Reading (UK) or Lausanne (Switzerland).
The responsibilities of the Analog Layout Engineer include:
* Work on the verification and layout of analog circuits focused on the IP for high-speed chip-to-chip links.
* Work closely with the design teams to implement solutions and understand design requirements.
* Help with the ongoing improvements of layout methodologies.
* Work closely with other teams in the business including the analog design team.
Additional requirements of the Analog Layout Engineer include:
* Experience with the layout of high speed circuits including PLL's and amplifiers.
* A technical understanding of the layout techniques and approaches for SerDes circuits.
* An understanding of the full product development life cycle and experience with tape-outs.
* Technical work on data-link transceivers.
* Ability to be based onsite and a user of EDA tools for verification and design e.g Cadence Virtuoso.
The successful analog layout engineer should be degree-qualified in electrical engineering or equivalent.
For further information, please contact Molly at IC Resources!