Lead Verification Engineer – SystemVerilog, UVM London, UK c£(Apply online only)k benefits This is an exciting and new opportunity for an experienced verification engineer to join a start-up involved with the research, development and design of technologies used to enhance, AI, ML and HPC networking. Our clients’ technologies will revolutionise data centres. Their technologies will speed up training and inference while dramatically reducing energy consumption, supporting a sustainable future. They are looking for a Verification Lead to work alongside a team of multi-skilled development engineers to verify their high-speed network interface card at the integrated system level, working iteratively through a series of prototypes to deliver a production-grade solution ultimately. Responsibilities will include defining the system-level verification strategy, coordinating test planning and implementation with the design team and external partners, and tracking progress to meet functional and code coverage metrics. There are two key elements to this role: 1. The creation, implementation and set up of appropriate verification infrastructure and environments 2. The planning and creation of test plans, which will include some hands-on verification activities and working with 3rd party suppliers Typical involvements: Lead Verification Engineer – SystemVerilog, UVM Verification strategy and architecture definition and documentation Planning and tracking functional and code coverage metrics Hands-on implementation of verification infrastructure and test cases, likely in SystemVerilog, alongside the design team and external partners Debugging failures, creating and tracking issues to closure. Creating and maintaining dashboards tracking the quality of the design. Creating and maintaining automated regression test infrastructure and gatekeepers Skills & Experience required: Lead Verification Engineer – SystemVerilog, UVM A Bachelor or Master degree in electronics engineering, physics, or other relevant fields c8-10 years of relevant experience working within verification of similar systems and technologies Experience of creating / implementing verification processes, infrastructure and environments Extensive hands-on industry experience of industry-standard verification best practices, including SystemVerilog. Strong knowledge of UVM (universal verification methodology) will be required. Experience of working with PCIe, CXL, RDMA, DDR4, Ethernet and IP technologies Understanding of mixed hardware/software verification techniques such as cosimulation and transation level modelling Knowledge of techniques for porting verification tests to real hardware Demonstrable ability to pragmatically work with designers to achieve verification goals with both quality and agility Excellent test automation and scripting experience Other skills / knowledge: A humble attitude and good communication skills with experience of working with external suppliers Ability to create an understanding of complex ideas, concepts and designs to a variety of audiences from multiple backgrounds A strong and demonstrable interest in sustainable technologies, AI, ML and / or HPC would be preferred. The Lead Verification Engineer opening is based on site in central London, 2 days per week (min). Assistance can be granted to obtain working visas