Job Description
Formal Verification Application Engineer – Cambridge
A market-leading EDA company is looking for an experienced Engineer to come and join their Application Engineering team in Cambridge. This is a fantastic opportunity for a Formal Verification Engineer to progress into a more customer-facing role as you will interact closely with the R&D team and the customer.
In this role you will have a fantastic opportunity to expand your Formal Verification skills and work closely with a leading-edge customer!
Requirements:
* Bachelor or Master in Electronic Engineering or a related field
* Proven technical experience in Jasper Gold, OneSpin, or VC Formal is essential
* Knowledge of Verilog, System Verilog or VHDL
* Involved in several tapeouts at multiple technology nodes
Email -
Tel - 01189073075
LinkedIn - -browne-b4a08b20b/