FPGA Design Engineer
Stevenage
SC required before starting Early Starter? No
6+ Months – Likely To Be Extended
Full Time ONSITE Role
PAY RATE: £70 - £90 + Per Hour Umbrella Inside IR35
FPGA design experience
FPGA verification experience
VHDL language skills
Overview of department:
For this role, we are seeking an experienced FPGA design and verification engineer (~4+ years), to support the development of our growing portfolio of complex FPGA projects. The current portfolio ranges from advanced signal processing systems (Image\Radio), core embedded processing systems, through to safety & security critical systems.
Responsibilities:
The role involves working at all phases of the FPGA design and verification cycle; hence, the candidate would be responsible some of the following key activities:
• Generating complex FPGA architectures and design implementations (VHDL, Simulink etc), targeting Xilinx, Intel, Microsemi devices.
• Verifying complex FPGA implementations using VHDL and System Verilog\UVM test-bench methodologies.
• Using FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim).
• Generating low-level software (C) to facilitate FPGA test and integration with the wider embedded system.
• Configuring and Documenting designs to a high professional standard.
• Working as part of a multidiscipline team to deliver complex FPGA based projects.
Skillset/experience required:
• Ideally we are looking for candidates that are degree qualified (or equivalent) with significant experience in FPGA development.
• Competent VHDL Language and Design Skills.
• Competent Verification Skills using VHDL and SystemVerilog methodologies
• A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs
• Experience of professionally configuring and documenting designs
• Experience of working as part of a large multidiscipline team
Job Info
Job Title:
Company:
CV-Library
Location:
Watford, Hertfordshire
Posted:
Closes:
Jan 6th 2025
Sector:
Military, Emergency & Government
Contract:
Contract
Hours:
Full Time
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