Hardware Verification Engineer (ASIC)
Grenoble / Paris (Hybrid 3 days a week on-site, 2 days a week wfh)
Up To €75,000
CDI Permanent Contract
Full-time
5V Tech is working in partnership with a leader in FPGA solutions, supporting them in looking for an ASIC Verification Engineer to join their hardware team.
You will shape verification standards, flows, and automation for RTL and Physical Implementation and will collaborate closely with RTL design, verification, and physical design engineers to deploy efficient, standardized solutions that elevate hardware engineering productivity.
Responsibilities:
1. Create and refine verification methodologies tailored to address challenges in clock domain crossings (CDC), reset domain crossings (RDC), and power domain crossings (PDC), ensuring optimal performance and reliability of designs.
2. Apply verification strategies to active FPGA projects, ensuring smooth integration of standardized solutions. Identify and resolve potential issues early in the design process.
3. Develop and maintain scripts and tools to automate verification processes, reducing manual intervention and improving team efficiency.
4. Create comprehensive documentation for verification techniques, workflows, and best practices, and ensure knowledge sharing through regular communication and training sessions.
Requirements:
1. Proven experience in hardware verification or design.
2. Strong understanding of power domains, clock domain crossings, clock and reset distribution, power simulation, and optimization.
3. Hands-on experience with EDA tools like Synopsys, Cadence, or Siemens EDA.
4. Proficient in hardware verification using Verilog/SystemVerilog.
5. Programming/scripting skills in Python, C/C++, TCL, or other relevant languages.
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