As a Lead RFIC Design Engineer, you are responsible for block level design in Ku/Ka band RF Transmitters and Receivers for the next generation of satellite communications in deep sub-micron technologies. You will handle architecture design, circuit design & verification, and review RFIC building blocks like PA, Active VGA, and Phase Shifters.
The job places you at the helm of ASIC development where you will develop new circuit architectures and design/verification methodologies to deliver ASICs that meet all performance requirements within the required timeline. While primarily owning block level designs, you will work closely with the layout engineer to ensure the layout meets all constraints for optimal silicon performance.
As a Lead Engineer, you will collaborate with chip leads in block level design reviews, top level verification, and with the test team in developing the test plan and characterizing the ASIC.
Technical Responsibilities:
* Responsible for architecture and circuit design for RFIC building blocks like PA, Phase Shifter, Active VGA.
* Deliver high-quality RF/Analog blocks with leading edge performance using innovative architectures and circuit implementations.
* Work closely with the layout team on IP floor-planning, trial layout design, parasitic extraction, and modifications.
* Coordinate design activities with colleagues.
* Document work and lead design reviews.
Organisational Responsibilities:
* Ongoing development of core competencies & technical skills.
* Receptive and agile to project needs.
* Good estimation of timescales for projects & sub-tasks.
* Follow good engineering practices including processes, documentation, tools & automation.
* Identify risks and flag issues in a timely manner to keep project milestones on schedule.
Qualifications & Skills:
* An Engineering degree in a relevant discipline.
* Minimum of 6 years’ experience in RFIC Design (preferably 15GHz or higher operating frequencies) – including 2 or more successful tape-outs.
* Excellent understanding of state-of-the-art RF CMOS circuit design and transceiver architectures – especially PA design.
* Experience designing high performance Analog/RF circuits in deep sub-micron technology with a strong analytical approach and a clear track record of success.
* Ability to work and interact with engineering teams across multiple disciplines during ASIC development.
* Great communication skills and responsibility for complex circuit and system designs and delivery to tight timescales.
* Experience in 22nm FDSOI or other sub 45nm CMOS process nodes for RF/High speed ICs.
* Experience with processes relating to production release and qualification.
* Experience in EM modelling tools such as RFPro or EMX.
* Experience in mmW/RF IC design.
* Understanding of Radio systems, gain and noise budgeting, phase noise, and intermodulation mechanisms.
* Experience in RFIC Characterisation.
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